The present invention relates to semiconductor memory devices and, more specifically, to metal-nitride-oxide-silicon (MNOS) memory devices.
The gate electrode of a conventional MNOS device consists of an evaporated layer of high-purity aluminum, usually as part of the metallization pattern employed in the integrated circuit which contains the MNOS memory. This aluminum is contiguous with the uppermost of a plurality of dielectric layers such as silicon nitride, silicon oxy-nitride, and silicon dioxide, which cover the silicon chip. In the memory gate areas, the lowermost or silicon dioxide layer is very thin, of the order of 20 A, which is conducive to tunneling of charges between the silicon and traps located in the dielectric adjacent to the silicon dioxide layer during application of a voltage pulse between the gate electrode and the silicon substrate. This tunneling mode of charge transport and storage is generally used in MNOS memory applications where long retention time is more important than ultra-fast writing and erasing. In order to maximize retention time, further trade-offs are involved in the choice of process parameters during the fabrication of the gate dielectric. Thus, for instance, as described in "Trap-assisted Charge Injection in MNOS Structures" by C. Svensson et al., J. App. Phys. 44, No. 10, p. 4662 (Oct. 1973), lower trap densities in the oxide-to-nitride interface region and correspondingly higher writing and erasing fields required for equal switching effects will yield longer retention.
A problem, however, arises as high fields are applied to a low-trap-density dielectric of maximum charge retention. The charging current by injection from the metal electrode and conduction through the nitride, between metal electrode and trapping layer, is no longer negligible compared to the charging current by tunneling through the thin oxide layer. The nitride current opposes the tunneling and, due to increasing nitride conductivity with increasing field, causes saturation, as is known from "Theory of the Maximum Charge Stored in the Thin Oxide MNOS Memory Transistor", C. Svensson, Proc. IEEE 59, p. 1135 (July, 1971) and from "Characterization of Thin-Oxide MNOS Memory Transistors", M. H. White et al., IEEE Trans. ED-19, No. 12, p. 1285 (Dec. 1972), and even reversal of the desired switching effect. As a result, the magnitude of the obtainable threshold shift may be insufficient. In case of p-channel devices, this limitation is serious with the pulse polarity used for "writing", i.e., with the negative potential applied to the gate electrode. Sufficiently high OFF-state thresholds thus may be difficult to attain. At the present state of the art the problem has been avoided by the choice of parameters in the fabrication process of the gate dielectric that tend to facilitate tunneling but entail a corresponding loss in retention.